System-on-Chip Test Architectures Nanometer Design for Testability Wang Volume .

System-on-Chip Test Architectures\nPlease note: \nthis item is printed on demand and will take extra time before it can be dispatched to you (up to 20 working days).\n\nNanometer Design for Testability\nAuthor(s): Laung-Terng Wang, Charles E. Stroud, Nur A. Touba\nFormat: Hardback\nPublisher: Elsevier Science & Technology, United States\nImprint: Morgan Kaufmann Publishers In\nISBN-13: 9780123739735, 978-0123739735\nSynopsis\nModern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V.