Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

CRC Press

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. \n\n--Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material\n--Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics \n--Reviews SDD testing based on \""alternative methods\"" th.

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