SystemVerilog for Verification by Chris Spear - 9781441945617

SystemVerilog for VerificationA Guide to Learning the Testbench Language Features\nAuthor(s): Chris Spear\nFormat: Paperback\nPublisher: Springer-Verlag New York Inc., United States\nImprint: Springer-Verlag New York Inc.\nISBN-13: 9781441945617, 978-1441945617\nSynopsis\nSystemVerilog for Verification, Second Edition provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog [url] constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog [url] topics such as interfaces and data types.\n\nThis second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch. Th""